Frequency synthesizers are often used when an electrical signal having a variable or controllable frequency is needed. For example, modern wireless communications systems may need to transmit data using different transmit channels having different frequencies. One traditional approach to providing a controllable frequency is a phase-locked loop (PLL).
FIG. 1 shows a traditional PLL 10 according to the prior art. The traditional PLL 10 includes a first voltage controlled oscillator (VCO) 12, a first fractional-N divider 14, a first phase/frequency detector 16, a first charge pump 18, and a first loop filter 20. The first VCO 12, the first fractional-N divider 14, the first phase/frequency detector 16, the first charge pump 18, and the first loop filter 20 forms a control loop having a loop gain and a loop bandwidth. The control loop uses a first reference signal VREF1 to synthesize a controlled oscillator output signal VCOOUT based on feeding back and frequency reducing the controlled oscillator output signal VCOOUT for comparison with the first reference signal VREF1.
The first VCO 12 provides the controlled oscillator output signal VCOOUT, which may be fed to other circuitry needing a controllable frequency signal. Additionally, the controlled oscillator output signal VCOOUT is fed to the first fractional-N divider 14, which is one form of frequency reduction circuitry. The first fractional-N divider 14 reduces the frequency of the controlled oscillator output signal VCOOUT by using digital divide circuitry to provide a first feedback signal VFB1, which has a frequency that is a fraction of the frequency of the controlled oscillator output signal VCOOUT. Traditional digital dividers typically divide a frequency of an input signal by an integer value. A fractional-N divider may be provided by varying or modulating the integer value to divide the frequency of the input signal by a value that is on average a fractional multiple of an integer.
The first feedback signal VFB1 is fed to the first phase/frequency detector 16. Additionally, the first reference signal VREF1 is fed to the first phase/frequency detector 16, which compares the first feedback signal VFB1 and the first reference signal VREF1 to provide a first phase-error signal VPES1 based on a phase difference or a frequency difference between the first feedback signal VFB1 and the first reference signal VREF1. The first phase-error signal VPES1 is fed to the first change pump 18, which applies gain to the first phase-error signal VPES1 to provide a first charge pump output signal ICPO1. The first charge pump output signal ICPO1 is fed to the first loop filter 20, which filters the first charge pump output signal ICPO1 to provide a first control signal VCS1 to the first VCO 12. The frequency of the controlled oscillator output signal VCOOUT is based on the first control signal VCS1.
As previously discussed, the first VCO 12, the first fractional-N divider 14, the first phase/frequency detector 16, the first charge pump 18, and the first loop filter 20 form a control loop having a loop gain and a loop bandwidth. The loop bandwidth may be determined primarily by a lowpass filter response from the first loop filter 20. The loop gain may be determined primarily by the first charge pump 18, which typically increases the loop gain, and the first fractional-N divider 14, which typically reduces the loop gain. To maintain loop stability, the loop bandwidth may need to be fairly narrow due to the reduction in the loop gain caused by the first fractional-N divider 14.
As wireless devices, such as cell phones, wireless personal digital assistants (PDAs), or the like, evolve and provide expanded feature sets, wireless communications protocols become increasingly complex and demanding in utilization of bandwidth. Sophisticated modulation methods are used to convey as much information as possible while using as little bandwidth as possible. For example, polar modulation methods, which use a combination of phase modulation and amplitude modulation to encode data, are using increasing numbers of constellation points to encode data. Some wireless communications systems phase-modulate PLLs inside the control loop to provide phase-modulated signals. The loop bandwidth of such PLLs must be wide enough to provide accurate phase modulation. However, the high in-band noise of some traditional PLLs may be too high to allow a wide enough loop bandwidth to support the required modulation bandwidth. Therefore, a PLL having a low in-band noise, allowing a wider loop bandwidth than a traditional PLL's loop bandwidth is needed.
FIG. 2 shows a fractional-N offset PLL (FNOPLL) 22 according to the prior art. Both the FNOPLL 22 and the traditional PLL 10 (FIG. 1) include the first VCO 12, the first fractional-N divider 14, the first phase/frequency detector 16, the first charge pump 18, and the first loop filter 20. However, in the FNOPLL 22, the first fractional-N divider 14 is moved outside the control loop and is replaced with a first radio frequency (RF) mixer circuit 24, which includes an RF mixer 26 and a sideband selection filter and buffer 28 in the control loop. A PLL having the RF mixer 26 is called an offset PLL or a translational PLL. The controlled oscillator output signal VCOOUT is fed to the RF mixer 26, which is one form of frequency reduction circuitry. The RF mixer 26 mixes the controlled oscillator output signal VCOOUT and a local oscillator (LO) output signal VLOOUT to provide an intermediate frequency (IF) signal VIF to the sideband selection filter and buffer 28. The IF signal VIF has two sideband components as a result of mixing the controlled oscillator output signal VCOOUT and the LO output signal VLOOUT. A frequency of one of the sideband components, called an upper sideband component, is equal to a sum of the frequencies of the controlled oscillator output signal VCOOUT and the LO output signal VLOOUT. A frequency of the other of the sideband components, called a lower sideband component, is equal to a difference of the frequencies of the controlled oscillator output signal VCOOUT and the LO output signal VLOOUT.
The sideband selection filter and buffer 28 removes the upper sideband component and provides a filtered IF signal VFIF based on buffering the lower sideband component. A LO 30 provides the LO output signal VLOOUT to the RF mixer 26 and to the first fractional-N divider 14, which reduces the frequency of the LO output signal VLOOUT by using digital divide circuitry to provide a divided LO signal VDLO, which has a frequency that is a fraction of the frequency of the LO output signal VLOOUT. The filtered IF signal VFIF and the divided LO signal VDLO are fed to the first phase/frequency detector 16, which compares the filtered IF signal VFIF and the divided LO signal VDLO to provide the first phase-error signal VPES1 based on a phase difference or a frequency difference between the filtered IF signal VFIF and the divided LO signal VDLO. The first phase-error signal VPES1 is fed to the first charge pump 18, which applies gain to the first phase-error signal VPES1 to provide the first charge pump output signal ICPO1. The first charge pump output signal ICPO1 is fed to the first loop filter 20, which filters the first charge pump output signal ICPO1 to provide the first control signal VCS1 to the first VCO 12. The frequency of the controlled oscillator output signal VCOOUT is based on the first control signal VCS1.
The filtered IF signal VFIF replaces the first feedback signal VFB1 (FIG. 1) and the divided LO signal VDLO replaces the first reference signal VREF1 (FIG. 1). A frequency of the divided LO signal VDLO is equal to the frequency of the LO output signal VLOOUT divided by an average division ratio associated with the first fractional-N divider 14. Since the average division ratio may be any value, within resolution, tolerance, and operating constraints, an average frequency of the divided LO signal VDLO may be any value. Therefore, the frequency of the controlled oscillator output signal VCOOUT may be any value, within resolution, tolerance, and operating constraints.
The first fractional-N divider 14 includes a divider 32, a delta-sigma modulator 34, and a summation circuit 36. The divider 32 receives the LO output signal VLOOUT and provides the divided LO signal VDLO based on dividing the LO output signal VLOOUT using a modulated division integer, which is provided by the summation circuit 36. The summation circuit 36 receives and adds a first fractional integer FFN-N and a modulation integer MN to provide the modulated division integer. The divided LO signal VDLO feeds a clock input CLK of the delta-sigma modulator 34, which receives a first fractional modulation numerator FFN-NUM and uses the divided LO signal VDLO to provide the modulation integer MN based on the first fractional modulation numerator FFN-NUM. The modulation integer MN is an integer that may toggle between two or more values with a duty-cycle. Both the duty-cycle and the integer values are based on the first fractional modulation numerator FFN-NUM and the divided LO signal VDLO. By combining the modulation integer MN and the first fractional integer FFN-N, the summation circuit 36 provides the modulated division integer to the divider 32.
Since the modulated division integer is modulated, the divided LO signal VDLO is also modulated, and since the division ratio is equal to the frequency of the LO output signal VLOOUT divided by the frequency of the divided LO signal VDLO, the division ratio is also modulated. However, the division ratio may average to any value within resolution and tolerance constraints. Normally, the frequency of modulation of the modulated division integer is greater than the loop bandwidth, such that the frequency of the controlled oscillator output signal VCOOUT is about constant when the first fractional modulation numerator FFN-NUM and the first fractional integer FFN-N are constant. Therefore, the frequency of the controlled oscillator output signal VCOOUT is based on the average division ratio.
The modulation associated with the first fractional-N divider 14 is generally used to select the average or center frequency associated with the controlled oscillator output signal VCOOUT; however, additional modulation for communication may be applied to the divider modulus to modulate the controlled oscillator output signal VCOOUT. Such a modulation must operate within the loop bandwidth to pass undistorted to the controlled oscillator output signal VCOOUT. The controlled oscillator output signal VCOOUT may be phase modulated, frequency modulated, or both, by varying the first fractional modulus numerator FFN-NUM, the first fractional integer FFN-N, or both. Since the loop bandwidth of the traditional PLL 10 (FIG. 1) may be fairly narrow to maintain stability due to the loop gain reduction associated with the first fractional-N divider 14 (FIG. 1), the traditional PLL 10 may be unusable for modulating the controlled oscillator output signal VCOOUT. However, the RF mixer 26 may not reduce the loop gain significantly; therefore, the loop bandwidth may be fairly wide while maintaining loop stability, such that the loop bandwidth may be wide enough to support modulation requirements of many wireless communications protocols.
FIG. 3 shows details of the LO 30 illustrated in FIG. 2 according to the prior art. The LO 30 is similar to the traditional PLL 10 illustrated in FIG. 1, and includes a second VCO 38, a second fractional-N divider 40, a second phase/frequency detector 42, a second charge pump 44, and a second loop filter 46, and has the LO output signal VLOOUT, a second feedback signal VFB2, a LO reference signal VLOREF, a second phase-error signal VPES2, a second charge pump output signal ICPO2, and a second control signal VCS2, respectively. An LO modulation numerator LO-NUM and a LO integer LO-N may be provided to the second fractional-N divider 40 to select a division ratio of the frequency of the LO output signal VLOOUT divided by the frequency of the second feedback signal VFB2.
While the FNOPLL 22 illustrated in FIG. 2 has advantages over the traditional PLL 10 illustrated in FIG. 1, the FNOPLL 22 may have challenges as wireless communications protocols evolve, modulation frequencies increase, and linearity and accuracy requirements increase. For example, at higher offset frequencies of the FNOPLL 22, a well-controlled notch may be required in a transfer function of the first loop filter 20 to suppress the modulated divider noise spectrum in the FNOPLL 22. To precisely control the frequency of the notch, components in the first loop filter 20 may need to be calibrated. Further, additional poles that may be required by the notch in the first loop filter 20 may mandate that a zero in the transfer function of the first loop filter 20 be a very low frequency in order to maintain loop stability. Calibration circuitry and circuitry mandated by the additional poles and a very low frequency zero may add cost, complexity, circuit area, power consumption, or any combination thereof. Additionally, phase detectors and charge pumps operating at higher frequencies may require closer tolerances and may be difficult to design, manufacture, or both. Thus, there is a need for a PLL that is better suited for the challenges presented by evolving wireless communication protocols, providing a low in-band noise allowing a wide loop bandwidth with reasonable cost and complexity.